1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a fabricating method thereof that makes a parasitic capacity of a thin film transistor uniform.
2. Description of the Related Art
A liquid crystal display controls the light transmittance of liquid crystal cells in accordance with video signals to display a picture. An active matrix type liquid crystal display, where a thin film transistor (TFT) is formed at each liquid crystal cell, is capable of displaying an image with a more vivid picture quality when displaying a motion picture as compared with a passive matrix type liquid crystal display.
FIG. 1 is a view representing a related art liquid crystal display.
Referring to FIG. 1, a liquid crystal display includes a liquid crystal display panel 2 of active matrix type, a data driver 6 for supplying data to data lines DL1 to DLm of the liquid crystal display panel 2, and a gate driver 4 for supplying scanning pulses to gate lines GL1 to GLn of the liquid crystal display panel 2. ‘Clc’ represents the equivalent capacitance of the liquid crystal cell in FIG. 1.
Liquid crystal is interposed between an upper glass substrate and a lower glass substrate of the liquid crystal display panel 2. An array of m×n liquid crystal cells Clc is arranged in a matrix type in the liquid crystal display panel 2. Also, in the liquid crystal display panel 2, m data lines DL1 to DLm cross n gate lines GL1 to GLn and a TFT is formed at every crossing thereof for driving the liquid crystal cell Clc. The TFT is turned on in response to the scanning pulse to supply the data from the data lines DL to DLm to the liquid crystal cell Clc.
Referring to FIG. 2, a gate electrode 11 of the TFT is connected to the gate lines GL1 to GLn along the same horizontal line. A source electrode 12 of the TFT is connected to the data lines DL1 to Dlm along the same vertical line. A drain electrode 13 of the TFT is connected to a pixel electrode of the liquid crystal cell Clc at every liquid crystal cell Clc.
In FIG. 1, a gate driver 4 generates scanning pulses under control of a timing controller (not shown) and sequentially supplies the scanning pluses to the gate lines GL1 to GLn. The gate driver 4 includes a shift register for sequentially generating the scanning pulses and a level shift for shifting the swing width of the voltage of the scanning pulse to be suitable for driving the liquid crystal cell Clc. The TFT is turned on in response to the scanning pulse from the gate driver 4. The video data on the data line DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc when the TFT is turned on.
The data driver 6 samples the video data inputted from the timing controller (not shown) and latches them, then it converts the latched data into a gamma correction voltage, which is set as a pixel data voltage beforehand, to supply to the data lines DL1 to DLm at the same time. Herein, the data converted by the data driver 6 are synchronized with each scanning pulse every time the scanning pulse is generated and supplied to the data lines DL1 to DLm by one horizontal line portion during one horizontal period.
FIG. 2 is a plan view representing an enlarged part of a TFT array formed on a lower glass substrate of a liquid crystal display panel.
FIG. 3 is a sectional view particularly representing the section of the TFT by cutting off along the line A-A′ in FIG. 2.
Referring to FIGS. 2 and 3, on a lower glass substrate 20 of the liquid crystal display panel, a TFT is formed at a crossing of the gate line 23 and the data line 24, a pixel electrode 19 is formed within the pixel area provided between the gate line 23 and the data line 24 and connected to the drain electrode 13 of the TFT. Also, a storage capacitor (CAP) is formed between the gate line 23 and the pixel electrode 19 on the lower glass substrate 20 of the liquid crystal display panel.
On the surface of the lower glass substrate 20, the gate electrode 11 of the TFT and the gate line 23 connected thereto are formed at the same time by depositing and patterning a metal. A projecting part 23a projected toward the pixel electrode 19 is formed at a lower side of the gate line 23. A gate insulating layer 16 of inorganic insulating material is formed on the entire surface of the lower glass substrate 20 and a gate metal layer including the gate electrode 11 and the gate line 23. A semiconductor layer 14 of semiconductor material is formed on the gate insulating layer 16 and then an ohmic contact layer 15, where the semiconductor material is doped with impurities, is deposited on top of the semiconductor layer 14.
On top of the ohmic contact layer 15 are formed the source electrode 12 of the TFT, the data line 24 connected thereto, and a drain electrode 13 facing the source electrode 12 with a specific channel in between. The source electrode 12 and the drain electrode 13 of the TFT overlaps with the gate electrode 11 while having the gate insulating layer 16, the semiconductor layer 14 and the ohmic contact layer 15 therebetween. A capacitor electrode 21 is formed to overlap with the projected part 23a of the gate line 23 at the same time as the data line 24, the source electrode 12 and the drain electrode 13 are formed.
The storage capacitor (CAP) has a gate line 23 and a capacitor electrode 21 overlapping with it and has a dielectric layer, i.e., the gate insulating layer 16 therebetween for being charged with voltage when a gate high voltage is applied to the previous gate line 23 and maintains the voltage charged until the data is inputted to the next frame, thereby restraining the voltage fluctuation of the pixel electrode 19.
In this way, after the TFT, the gate line 23 and the data line 24 are formed, a passivation layer 17 of inorganic insulating material or organic insulating material is formed on the entire surface of the lower glass substrate 20. A contact hole 18 for exposing part of the drain electrode 13 and a contact hole 22 for exposing part of the capacitor electrode 21 are formed in the passivation layer 17.
A pixel electrode 19 of transparent conductive material such as indium-tin-oxide (ITO) etc. is formed on the passivation layer 17. A projecting part 23a of the gate line is formed on the upper end of the pixel electrode 19 and a projecting part 19a of the pixel electrode 19 both overlap with the capacitor electrode 21. The pixel electrode 19 is connected to the drain electrode 13 and the capacitor electrode 22 via the contact holes 18 and 22.
Voltage Vp is applied to the liquid crystal cell of the liquid crystal display panel as in the following Formula 1.ΔVp=(Cgs/Clc+Cst+Cgs)×ΔVg  [FORMULA 1]
Herein, Cgs is a capacitance between the gate electrode 11 and the source electrode 12 of the TFT or the gate electrode 11 and the drain electrode 13 of the TFT, Cst is a capacitance of the storage capacitor (CAP), and ΔVg represents a potential difference between a gate high voltage and a gate low voltage of the scanning pulse supplied to the gate line 23.
As seen in Formula 1, when the same data voltage is supplied, for the voltage Vp applied to each liquid crystal cell Clc of the liquid crystal panel, the gate-source capacitance Cgs, the scanning voltage ΔVg, the capacitance Cst of the storage capacitor, and the capacitance Clc of the liquid crystal cell should be made the same. In the gate-source capacitance Cgs, it is possible to have a deviation because a mask is not aligned correctly when the source electrode 12 and the drain electrode 13 of the TFT are patterned using a photolithography process. In this case, because the voltage applied to the liquid crystal cell Clc is changed, the light transmittance of the liquid crystal cell Clc is changed to generate flickers, thereby deteriorating display quality.